In the fabrication of semiconductor integrated circuits, metal conductor lines are used to interconnect the multiple components in device circuits on a semiconductor wafer. A general process used in the deposition of metal conductor line patterns on semiconductor wafers includes deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal conductor line pattern, using standard lithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby leaving the metal layer in the form of the masked conductor line pattern; and removing the mask layer typically using reactive plasma and chlorine gas, thereby exposing the top surface of the metal conductor lines. Typically, multiple alternating layers of electrically conductive and insulative materials are sequentially deposited on the wafer substrate, and conductive layers at different levels on the wafer may be electrically connected to each other by etching vias, or openings, in the insulative layers and filling the vias using aluminum, tungsten or other metal to establish electrical connection between the conductive layers.
A current drive in the semiconductor device industry is to produce semiconductors having an increasingly large density of integrated circuits which are ever-decreasing in size. These goals are achieved by scaling down the size of the circuit features in both the lateral and vertical dimensions. Vertical downscaling requires that the thickness of gate oxides on the wafer be reduced by a degree which corresponds to shrinkage of the circuit features in the lateral dimension. While there are still circumstances in which thicker gate dielectrics on a wafer are useful, such as to maintain operating voltage compatibility between the device circuits manufactured on a wafer and the current packaged integrated circuits which operate at a standard voltage, ultrathin gate dielectrics will become increasingly essential for the fabrication of semiconductor integrated circuits in the burgeoning small/fast device technology.
In micro-electromechanical systems (MEMS) and other technologies, voids may be intentionally formed in a substrate to create controlled micro channel structures. In integrated circuit fabrication, these micro channels or pipes may be used to cool the substrate or semiconductor devices fabricated thereon. In addition, micro pipes may be fabricated on substrates and used as channels for fluid control and movement.
Micro pipes are conventionally formed on a substrate by initially forming a V-shaped or U-shaped groove in the substrate. The groove is then covered with a layer of lid-glass. However, this technique is sometimes difficult to carry out and is unsuitable for fabrication of multi-layered micro piping.
Another method of manufacturing and using micro pipe systems is disclosed in U.S. Pat. Nos. 6,031,286 and 6,228,744, both assigned to IBM. According to that method, micro pipes are fabricated in a semiconductor device or other suitable substrate by controlling the aspect ratio of trenches as well as controlling the deposition characteristics of the material used to fill the trenches. A buried micro pipe is formed by filling a trench that has a height which is larger than a width thereof, so that the trench filler material lines sidewalls and bottom of the trench, and covers the top of the trench to form the micro pipe within the trench. Another layer can be formed over the filler material and planarized. Alternatively, the filler material itself can be planarized. Forming trenches in the planarized layer and repeating the above steps forms a second set of buried micro pipes in these new trenches. This forms a semiconductor device having multiple layer of buried micro pipes. Via holes may be etched to contact a micro pipe, or to interconnect micro pipes buried at different levels. Thus, instead of eliminating defective voids in trenches, the voids are controlled to form the micro pipes, which may be used to circulate a cooling fluid, or lined with a conductive material to form a micro light pipe channel or buried conductive pipes.
One of the limitations inherent in the conventional methods of fabricating micro pipes is that the methods are unsuitable for fabricating relatively large micro pipes of a size on the order of about 30˜200 m in diameter. Accordingly, an improved micro pipe fabrication method is needed which is easy to carry out, applicable to a variety of technologies and is capable of fabricating multi-layered and larger-sized micro pipes.
An object of the present invention is to provide an improved method for fabricating micro pipes on a substrate.
Another object of the present invention is to provide an improved method which is capable of fabricating multiple layers of micro pipes on a substrate.
Still another object of the present invention is to provide an improved micro pipe fabrication method which is easy to carry out.
Yet another object of the present invention is to provide an improved micro pipe fabrication method which is suitable for fabricating micro pipes on the order of about 30˜200 m in diameter.
A still further object of the present invention is to provide an improved micro pipe fabrication method which is applicable to semiconductor fabrication as well as biotech or other technologies.